A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

Masoud Nouripayam; Joachim Rodrigues; Xiao Luo; Tom Johansson; Babak Mohammadi

doi:10.1109/ESSCIRC53450.2021.9567785

A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

Masoud Nouripayam, Joachim Rodrigues, Xiao Luo, Tom Johansson, Babak Mohammadi

Xenergic AB

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.

Original language	English
Title of host publication	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	459-462
Number of pages	4
ISBN (Electronic)	978-1-6654-3751-6
DOIs	https://doi.org/10.1109/ESSCIRC53450.2021.9567785
Publication status	Published - 2021 Sept 13
Event	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 - Virtual, Online, France Duration: 2021 Sept 6 → 2021 Sept 9

Publication series

Name	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

Conference

Conference	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021
Country/Territory	France
City	Virtual, Online
Period	2021/09/06 → 2021/09/09

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

6T bitcell
boost-assist
dual-port
low-power
low-voltage
single-ended read
SRAM

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ESSCIRC53450.2021.9567785

Cite this

Nouripayam, M., Rodrigues, J., Luo, X., Johansson, T., & Mohammadi, B. (2021). A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp. 459-462). (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings). IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC53450.2021.9567785

Nouripayam, Masoud ; Rodrigues, Joachim ; Luo, Xiao et al. / A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc., 2021. pp. 459-462 (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).

@inproceedings{8b32eb8d6b4e481cad3b429a2962e870,

title = "A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI",

abstract = "A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V. ",

keywords = "6T bitcell, boost-assist, dual-port, low-power, low-voltage, single-ended read, SRAM",

author = "Masoud Nouripayam and Joachim Rodrigues and Xiao Luo and Tom Johansson and Babak Mohammadi",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 ; Conference date: 06-09-2021 Through 09-09-2021",

year = "2021",

month = sep,

day = "13",

doi = "10.1109/ESSCIRC53450.2021.9567785",

language = "English",

series = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "459--462",

booktitle = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings",

address = "United States",

}

Nouripayam, M , Rodrigues, J, Luo, X, Johansson, T & Mohammadi, B 2021, A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 459-462, 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Virtual, Online, France, 2021/09/06. https://doi.org/10.1109/ESSCIRC53450.2021.9567785

A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. / Nouripayam, Masoud ; Rodrigues, Joachim; Luo, Xiao et al.
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc., 2021. p. 459-462 (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

AU - Nouripayam, Masoud

AU - Rodrigues, Joachim

AU - Luo, Xiao

AU - Johansson, Tom

AU - Mohammadi, Babak

PY - 2021/9/13

Y1 - 2021/9/13

N2 - A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.

AB - A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.

KW - 6T bitcell

KW - boost-assist

KW - dual-port

KW - low-power

KW - low-voltage

KW - single-ended read

KW - SRAM

U2 - 10.1109/ESSCIRC53450.2021.9567785

DO - 10.1109/ESSCIRC53450.2021.9567785

M3 - Paper in conference proceeding

AN - SCOPUS:85118430844

T3 - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

SP - 459

EP - 462

BT - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021

Y2 - 6 September 2021 through 9 September 2021

ER -

Nouripayam M , Rodrigues J, Luo X, Johansson T, Mohammadi B. A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc. 2021. p. 459-462. (ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings). doi: 10.1109/ESSCIRC53450.2021.9567785

A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

Abstract

Publication series

Conference

Subject classification (UKÄ)

Free keywords

UN SDGs

Access to Document

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Cite this