A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

Seiko Netsu; Markus Hellenbrand; Cezar B. Zota; Yasuyuki Miyamoto; Erik Lind

doi:10.1109/JEDS.2018.2806487

A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

Seiko Netsu, Markus Hellenbrand, Cezar B. Zota, Yasuyuki Miyamoto, Erik Lind

Tokyo Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

Original language	English
Pages (from-to)	408-412
Journal	IEEE Journal of the Electron Devices Society
Volume	6
Early online date	2018 Feb 16
DOIs	https://doi.org/10.1109/JEDS.2018.2806487
Publication status	Published - 2018

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Electron traps
FinFETs.
high-κ
Hysteresis
hysteresis
III-V
InGaAs
inter face trap
Logic gates
Mathematical model
MOSFET
MOSFETs
Multi-gate
Surface fitting
Surface treatment
trap density

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10.1109/JEDS.2018.2806487

2 Doctoral Thesis (compilation)

Electrical Characterisation of III-V Nanowire MOSFETs
Hellenbrand, M., 2020 May, Lund: Department of Electrical and Information Technology, Lund University. 156 p.
Research output: Thesis › Doctoral Thesis (compilation)

Open Access
File
III-V MOSFETs for High-Frequency and Digital Applications
Zota, C., 2017 Apr 10, Department of Electrical and Information Technology, Lund University.
Research output: Thesis › Doctoral Thesis (compilation)

Open Access
File

Cite this

@article{5f2f837d3a8c406fa1e48e37b75d5c28,

title = "A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs",

abstract = "We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.",

keywords = "Electron traps, FinFETs., high-κ, Hysteresis, hysteresis, III-V, InGaAs, inter face trap, Logic gates, Mathematical model, MOSFET, MOSFETs, Multi-gate, Surface fitting, Surface treatment, trap density",

author = "Seiko Netsu and Markus Hellenbrand and Zota, {Cezar B.} and Yasuyuki Miyamoto and Erik Lind",

year = "2018",

doi = "10.1109/JEDS.2018.2806487",

language = "English",

volume = "6",

pages = "408--412",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

AU - Netsu, Seiko

AU - Hellenbrand, Markus

AU - Zota, Cezar B.

AU - Miyamoto, Yasuyuki

AU - Lind, Erik

PY - 2018

Y1 - 2018

N2 - We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

AB - We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

KW - Electron traps

KW - FinFETs.

KW - high-κ

KW - Hysteresis

KW - hysteresis

KW - III-V

KW - InGaAs

KW - inter face trap

KW - Logic gates

KW - Mathematical model

KW - MOSFET

KW - MOSFETs

KW - Multi-gate

KW - Surface fitting

KW - Surface treatment

KW - trap density

U2 - 10.1109/JEDS.2018.2806487

DO - 10.1109/JEDS.2018.2806487

M3 - Article

AN - SCOPUS:85042179791

SN - 2168-6734

VL - 6

SP - 408

EP - 412

JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

ER -

A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

Abstract

Subject classification (UKÄ)

Free keywords

Access to Document

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Research output

Electrical Characterisation of III-V Nanowire MOSFETs

III-V MOSFETs for High-Frequency and Digital Applications

Cite this