Abstract
Abstract in Undetermined
In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bit-parallel respectively bit-serial architecture. The paper shows a substantial reduction of the static power consumption when bit-serial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used word length, i.e. the reduction is larger for longer word lengths. The reduction is dependent on the ratio between the arithmetic and the storage (the registers) as well. Architectures where the arithmetic dominates will show a larger reduction of the static power consumption. A static power reduction down to 37 % is shown for the bit-serial filter architecture and a reduction down to 7 % is shown in the arithmetic in the filter.
In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bit-parallel respectively bit-serial architecture. The paper shows a substantial reduction of the static power consumption when bit-serial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used word length, i.e. the reduction is larger for longer word lengths. The reduction is dependent on the ratio between the arithmetic and the storage (the registers) as well. Architectures where the arithmetic dominates will show a larger reduction of the static power consumption. A static power reduction down to 37 % is shown for the bit-serial filter architecture and a reduction down to 7 % is shown in the arithmetic in the filter.
Original language | English |
---|---|
Title of host publication | International Conference on Microelectronics ICM |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Pages | 11-14 |
Number of pages | 4 |
ISBN (Print) | 978-1-4244-2369-9 |
DOIs | |
Publication status | Published - 2008 |
Event | The 20th International Conference on Microelectronics (ICM'08) - Sharjah, United Arab Emirates Duration: 2008 Dec 14 → 2008 Dec 17 |
Conference
Conference | The 20th International Conference on Microelectronics (ICM'08) |
---|---|
Country/Territory | United Arab Emirates |
City | Sharjah |
Period | 2008/12/14 → 2008/12/17 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering