Abstract
A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.
| Original language | English |
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| Title of host publication | [Host publication title missing] |
| Pages | 766-770 |
| DOIs | |
| Publication status | Published - 1996 |
| Event | The 10th International Parallel Processing Symposium, 1996., IPPS '96 - Honolulu, HI, United States Duration: 1996 Apr 15 → 1996 Apr 19 |
Conference
| Conference | The 10th International Parallel Processing Symposium, 1996., IPPS '96 |
|---|---|
| Country/Territory | United States |
| City | Honolulu, HI |
| Period | 1996/04/15 → 1996/04/19 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- pipeline processing
- parallel architectures
- parallel algorithms
- microprocessor chips
- hardware description languages
- feedback
- fast Fourier transforms
- divide and conquer methods
- discrete Fourier transforms
- delay systems
- VLSI
- computational complexity
- real-time systems