Abstract
This paper presents a low complexity, yet power efficient technique to boost the flexibility of a pipelined ADC. It also presents an implementation proposal with simulated results for a reconfigurable pipelined ADC. The proposed ADC architecture is a combination of the conventional pipelined ADC and the cyclic ADC, giving it a very low level of complexity, a high level of component reuse and substantial power savings in low speed low accuracy modes.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the IASTED International Conference on Circuits, Signals, and Systems |
| Publisher | ACTA Press |
| Pages | 199-204 |
| ISBN (Print) | 0889864551 |
| Publication status | Published - 2004 |
| Event | IASTED International Conference on Circuits, Signals, and Systems, 2004 - Clearwater Beach, FL, United States Duration: 2004 Nov 28 → 2004 Dec 1 |
Conference
| Conference | IASTED International Conference on Circuits, Signals, and Systems, 2004 |
|---|---|
| Country/Territory | United States |
| City | Clearwater Beach, FL |
| Period | 2004/11/28 → 2004/12/01 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- Pipelined flexible
- Reconfigurable
- Mobile terminal
- ADC