A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Andreas Axholt, Henrik Sjöland

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


A 12 GHz PLL with digital output phase control
has been implemented in a 90 nm CMOS process. It is intended
for LO signal generation in integrated phased array transceivers.
Locally placed PLLs eliminate the need of long high frequency
LO routing to each transceiver in a phased array circuit.
Routing losses are thereby reduced and design of integrated
phased array transceivers become more modular. A chip was
manufactured, featuring two separate fully integrated PLLs
operating at 12 GHz, with a common 1.5 GHz reference. The chip,
including pads, measures 1050x700 μm2. Each PLL consumes
15 mA from a 1.2 V supply, with a typical measured phase noise
of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds
Original languageEnglish
Title of host publicationProc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore
Publication statusPublished - 2009
EventAsia Pacific Microwave Conference, APMC 2009 - Singapore, Singapore
Duration: 2009 Dec 7 → …


ConferenceAsia Pacific Microwave Conference, APMC 2009
Period2009/12/07 → …

Bibliographical note

Best paper award Active circuits (APMC Price)

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • Phase locked loops
  • Beam steering
  • CMOS analog integrated circuits.
  • Array signal processing
  • Millimeter wave antenna arrays


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