Abstract
We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.
| Original language | English |
|---|---|
| Title of host publication | [Host publication title missing] |
| Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| Pages | 26 |
| Publication status | Published - 2000 |
| Externally published | Yes |
| Event | Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS - Duration: 0001 Jan 2 → … |
Conference
| Conference | Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS |
|---|---|
| Period | 0001/01/02 → … |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- testing
- simulated annealing
- test scheduling
- test bus infrastructure