TY - GEN
T1 - A two-stage mm-wave PA with 18.5% PAE in 65 nm CMOS
AU - Forsberg, Therese
AU - Sjöland, Henrik
AU - Törmänen, Markus
PY - 2015
Y1 - 2015
N2 - A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB, a 1dB-compression point (P1dB) of 8.4 dBm and a saturated output power (Psat) of 11.8dBm, with a peak power added efficiency (PAE) of 18.5 %. The PA core occupies an area of 100 um x 300 um.
AB - A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB, a 1dB-compression point (P1dB) of 8.4 dBm and a saturated output power (Psat) of 11.8dBm, with a peak power added efficiency (PAE) of 18.5 %. The PA core occupies an area of 100 um x 300 um.
U2 - 10.1109/APMC.2015.7411664
DO - 10.1109/APMC.2015.7411664
M3 - Paper in conference proceeding
SN - 978-1-4799-8765-8
VL - 1
SP - 1
EP - 3
BT - 2015 Asia-Pacific Microwave Conference (APMC)
T2 - 2015 Asia-Pacific Microwave Conference (APMC)
Y2 - 6 December 2015 through 9 December 2015
ER -