A unified approach to constrained mapping and routing on network-on-chip architectures

A Hansson; K Goossens; A Radulescu

doi:10.1145/1084834.1084857

A unified approach to constrained mapping and routing on network-on-chip architectures

A Hansson, K Goossens, A Radulescu

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach

Original language	English
Title of host publication	International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	75-80
ISBN (Print)	1-59593-161-9
DOIs	https://doi.org/10.1145/1084834.1084857
Publication status	Published - 2005
Externally published	Yes
Event	International Conference on Hardware/Software Codesign and System Synthesis - Jersey City, NJ, United States Duration: 2005 Sept 18 → 2005 Sept 21

Conference

Conference	International Conference on Hardware/Software Codesign and System Synthesis
Country/Territory	United States
City	Jersey City, NJ
Period	2005/09/18 → 2005/09/21

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

MPEG decoder system-on-chip
TDMA time-slot allocation
slot allocation
network routing
unified mapping
route communication
spatial mapping
constrained mapping
network-on-chip architectures

Access to Document

10.1145/1084834.1084857

Cite this

@inproceedings{d52569dc202e4b34afbb0b55f21fbf1c,

title = "A unified approach to constrained mapping and routing on network-on-chip architectures",

abstract = "One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach",

keywords = "MPEG decoder system-on-chip, TDMA time-slot allocation, slot allocation, network routing, unified mapping, route communication, spatial mapping, constrained mapping, network-on-chip architectures",

author = "A Hansson and K Goossens and A Radulescu",

year = "2005",

doi = "10.1145/1084834.1084857",

language = "English",

isbn = "1-59593-161-9",

pages = "75--80",

booktitle = "International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "International Conference on Hardware/Software Codesign and System Synthesis ; Conference date: 18-09-2005 Through 21-09-2005",

}

Hansson, A, Goossens, K & Radulescu, A 2005, A unified approach to constrained mapping and routing on network-on-chip architectures. in International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852). IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 75-80, International Conference on Hardware/Software Codesign and System Synthesis, Jersey City, NJ, United States, 2005/09/18. https://doi.org/10.1145/1084834.1084857

A unified approach to constrained mapping and routing on network-on-chip architectures. / Hansson, A; Goossens, K; Radulescu, A.
International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852). IEEE - Institute of Electrical and Electronics Engineers Inc., 2005. p. 75-80.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - A unified approach to constrained mapping and routing on network-on-chip architectures

AU - Hansson, A

AU - Goossens, K

AU - Radulescu, A

PY - 2005

Y1 - 2005

N2 - One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach

AB - One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach

KW - MPEG decoder system-on-chip

KW - TDMA time-slot allocation

KW - slot allocation

KW - network routing

KW - unified mapping

KW - route communication

KW - spatial mapping

KW - constrained mapping

KW - network-on-chip architectures

U2 - 10.1145/1084834.1084857

DO - 10.1145/1084834.1084857

M3 - Paper in conference proceeding

SN - 1-59593-161-9

SP - 75

EP - 80

BT - International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - International Conference on Hardware/Software Codesign and System Synthesis

Y2 - 18 September 2005 through 21 September 2005

ER -

A unified approach to constrained mapping and routing on network-on-chip architectures

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Cite this