Abstract
This paper discusses design and measurements of
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.
Flexibility was incorporated by providing various code rates and
modulation schemes to adjust to varying channel conditions.
Based on previous trade-off studies, flexible building blocks were
carefully designed to cause as little area penalty as possible. The
chip runs down to a minimal core supply of 0.8V. It turns out that
striving for more modulation schemes is beneficial in terms of
power consumption once the price is paid for accepting different
code rates viz. radices in the trellis and survivor path units.
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.
Flexibility was incorporated by providing various code rates and
modulation schemes to adjust to varying channel conditions.
Based on previous trade-off studies, flexible building blocks were
carefully designed to cause as little area penalty as possible. The
chip runs down to a minimal core supply of 0.8V. It turns out that
striving for more modulation schemes is beneficial in terms of
power consumption once the price is paid for accepting different
code rates viz. radices in the trellis and survivor path units.
| Original language | English |
|---|---|
| Title of host publication | Proceedings, Norchip Conference |
| Pages | 137-141 |
| Number of pages | 5 |
| Publication status | Published - 2008 |
| Event | Norchip Conference, 2008 - Tallinnn, Talinn, Estonia Duration: 2008 Nov 16 → 2008 Nov 17 |
Conference
| Conference | Norchip Conference, 2008 |
|---|---|
| Country/Territory | Estonia |
| City | Talinn |
| Period | 2008/11/16 → 2008/11/17 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- Viterbi decoder
- CMOS
- flexible chips
- integrated circuits