Abstract
This paper describes a VLSI implementation of V-BLAST detection for future multiple-input-multiple-output (MIMO) wireless communications. This design is implemented using a 0.35-μm 5-layer metal 3.3 V CMOS technology. For a 4-transmit and 4-receive antennas system using QPSK modulation scheme, a detecting throughput of 128 Mb/s can be achieved. Furthermore, it is shown that the implementation complexity can be reduced further to meet the requirements for future high speed downlink packet access (HSDPA) systems with MIMO extensions in 3<sup>rd</sup> generation (3G) mobile wireless systems
Original language | English |
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Title of host publication | 14th IEEE 2003 International Symposium on Personal, Indoor and Mobile Radio Communications. Proceedings (IEEE Cat. No.03TH8677) |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Pages | 2852-2856 |
ISBN (Print) | 0-7803-7822-9 |
DOIs | |
Publication status | Published - 2003 |
Event | 14th IEEE 2003 International Symposium on Personal, Indoor and Mobile Radio Communications. Proceedings - Beijing, China Duration: 2003 Sept 7 → 2003 Sept 10 |
Conference
Conference | 14th IEEE 2003 International Symposium on Personal, Indoor and Mobile Radio Communications. Proceedings |
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Country/Territory | China |
City | Beijing |
Period | 2003/09/07 → 2003/09/10 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- metal CMOS technology
- transmit antenna
- receive antenna
- QPSK modulation scheme
- 128 Mbit/s
- 3.3 V
- 0.35 micron
- high speed downlink packet access system
- 3G mobile wireless system
- vertical-Bell-Labs-layered-space-time detection
- VLSI implementation
- wireless communication
- MIMO detection
- multiple-input-multiple-output wireless communication