Abstract
The long andincreasing test application time for modular core-basedsystem-on-chips is a major problem, and many approaches have beendeveloped to deal with the problem. Different from previousapproaches, where it is assumed that all tests will be performeduntil completion, we consider the cases where the test process isterminated as soon as a defect is detected. Such abort-on-failtesting is common practice in production test of chips. We define amodel to compute the expected test time for a given test schedulein an abort-on-fail environment. We have implemented threescheduling techniques and the experimental results show asignificant test time reduction (up to 90%) when making use of anefficient test scheduling technique that takes defect probabilitiesinto account.
Original language | English |
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Pages (from-to) | 651-658 |
Journal | Journal of Electronic Testing |
Volume | 21 |
Issue number | 6 |
DOIs | |
Publication status | Published - 2005 |
Externally published | Yes |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- testing
- test scheduling
- abort-on-fail