Embedded Tutorial: Access to On-chip Instruments via Functional Ports

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

Semiconductor technology constantly advances, enabling integrated circuits (ICs) with increasingly numerous, faster, and smaller transistors. While this progress offers many benefits, it also presents new challenges, such as tighter margins, wear-outs, and process variations. To effectively tackle these challenges, the conventional approach of using external test instruments during manufacturing testing must be complemented with on-chip instruments. These on-chip instruments facilitate the detection of defects that emerge over the operational lifetime of the IC. Accessing on-chip instruments poses a challenge. We will discuss traditional test access method (IEEE Std. 1149.1 (JTAG)), reconfigurable scan networks (IEEE Std. 1687 (IJTAG)) and ongoing developments using functional ports to access test instruments (IEEE Std. P1687.1 and IEEE Std. P2654).
Original languageEnglish
Title of host publication2024 IEEE 25th Latin American Test Symposium (LATS)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages1-2
ISBN (Electronic)979-8-3503-6555-9
DOIs
Publication statusPublished - 2024 Apr 9
Event2024 IEEE 25th Latin American Test Symposium (LATS) - Maceio, Brazil
Duration: 2024 Apr 92024 Apr 12

Conference

Conference2024 IEEE 25th Latin American Test Symposium (LATS)
Period2024/04/092024/04/12

Subject classification (UKÄ)

  • Computer Engineering

Fingerprint

Dive into the research topics of 'Embedded Tutorial: Access to On-chip Instruments via Functional Ports'. Together they form a unique fingerprint.

Cite this