An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

Xiaodong Liu, Mattias Andersson, Martin Anderson, Lars Sundstrom, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingResearchpeer-review

3 Citations (SciVal)

Abstract

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.
Original languageEnglish
Title of host publication2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages2337-2340
Publication statusPublished - 2014
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2014 - Melbourne, Austrailia, Melbourne, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

Name
ISSN (Print)2158-1525
ISSN (Electronic)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2014
Country/TerritoryAustralia
CityMelbourne
Period2014/06/012014/06/05

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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