An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

Xiaodong Liu; Mattias Andersson; Martin Anderson; Lars Sundstrom; Pietro Andreani

An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

Xiaodong Liu, Mattias Andersson, Martin Anderson, Lars Sundstrom, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

Original language	English
Title of host publication	2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	2337-2340
Publication status	Published - 2014
Event	IEEE International Symposium on Circuits and Systems (ISCAS), 2014 - Melbourne, Austrailia, Melbourne, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name
ISSN (Print)	2158-1525
ISSN (Electronic)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS), 2014
Country/Territory	Australia
City	Melbourne
Period	2014/06/01 → 2014/06/05

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Cite this

@inproceedings{32c2ade94c91449ba11b87c093263ce3,

title = "An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS",

abstract = "This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.",

author = "Xiaodong Liu and Mattias Andersson and Martin Anderson and Lars Sundstrom and Pietro Andreani",

year = "2014",

language = "English",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "2337--2340",

booktitle = "2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS), 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

Liu, X, Andersson, M, Anderson, M, Sundstrom, L & Andreani, P 2014, An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS. in 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 2337-2340, IEEE International Symposium on Circuits and Systems (ISCAS), 2014, Melbourne, Australia, 2014/06/01.

An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS. / Liu, Xiaodong; Andersson, Mattias; Anderson, Martin et al.
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. p. 2337-2340.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

AU - Liu, Xiaodong

AU - Andersson, Mattias

AU - Anderson, Martin

AU - Sundstrom, Lars

AU - Andreani, Pietro

PY - 2014

Y1 - 2014

N2 - This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

AB - This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

M3 - Paper in conference proceeding

SP - 2337

EP - 2340

BT - 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Y2 - 1 June 2014 through 5 June 2014

ER -

An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

Abstract

Publication series

Conference

Subject classification (UKÄ)

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