An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS

Feifei Zhang; Peng Chen; Jeffrey S. Walling; Anding Zhu; Robert Bogdan Staszewski

doi:10.1109/TCSI.2021.3059368

An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS

Feifei Zhang, Peng Chen, Jeffrey S. Walling, Anding Zhu, Robert Bogdan Staszewski

Integrated Electronic Systems

Research output: Contribution to journal › Article › peer-review

Abstract

This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

Original language	English
Article number	9361220
Pages (from-to)	1855-1868
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	68
Issue number	5
DOIs	https://doi.org/10.1109/TCSI.2021.3059368
Publication status	Published - 2021 May

Bibliographical note

Funding Information:
Manuscript received June 4, 2020; revised November 3, 2020 and January 18, 2021; accepted February 7, 2021. Date of publication February 23, 2021; date of current version April 27, 2021. This work was supported by the Microelectronic Circuits Centre Ireland (MCCI) through Enterprise Ireland under Grant TC-2015-0019. This article was recommended by Associate Editor H. Stratigopoulos. (Corresponding author: Peng Chen.) Feifei Zhang was with MCCI, Dublin D04, Ireland, and also with the School of Electrical and Electronic Engineering, University College Dublin, Dublin D04, Ireland. She is now with Silicon Austria Labs, 4040 Linz, Austria (e-mail: [email protected]).

Publisher Copyright:
© 2004-2012 IEEE.

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Active-under-coil integration
Analog linear interpolation (ALI)
Class-E power amplifier
Multi-port transformer
RFDAC

Access to Document

10.1109/TCSI.2021.3059368Licence: CC BY

Cite this

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title = "An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS",

abstract = "This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.",

keywords = "Active-under-coil integration, Analog linear interpolation (ALI), Class-E power amplifier, Multi-port transformer, RFDAC",

author = "Feifei Zhang and Peng Chen and Walling, {Jeffrey S.} and Anding Zhu and Staszewski, {Robert Bogdan}",

note = "Funding Information: Manuscript received June 4, 2020; revised November 3, 2020 and January 18, 2021; accepted February 7, 2021. Date of publication February 23, 2021; date of current version April 27, 2021. This work was supported by the Microelectronic Circuits Centre Ireland (MCCI) through Enterprise Ireland under Grant TC-2015-0019. This article was recommended by Associate Editor H. Stratigopoulos. (Corresponding author: Peng Chen.) Feifei Zhang was with MCCI, Dublin D04, Ireland, and also with the School of Electrical and Electronic Engineering, University College Dublin, Dublin D04, Ireland. She is now with Silicon Austria Labs, 4040 Linz, Austria (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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N2 - This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

AB - This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

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An active-under-coil RFDAC with analog linear interpolation in 28-nm CMOS

Abstract

Bibliographical note

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