An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

Reza Meraji; John B Anderson; Henrik Sjöland; Viktor Öwall

doi:10.1109/ISCAS.2011.5938233

An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

Reza Meraji, John B Anderson, Henrik Sjöland, Viktor Öwall

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A complete architecture with transistor level simulation is
presented for a low power analog convolutional decoder in 65 nm CMOS.
The decoder core operates in the weak inversion (sub-VT) and realizes the
BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of
a (7,5) convolutional code. The complete decoder also incorporates serial
I/O digital interfaces and current mode differential DACs. The simulated
bit error rate is presented to illustrate the coding gain compared to an
uncoded system. Our results show that a low power, high throughput
convolutional decoder up to 1.25 Mb/s can be implemented using analog
circuitry with a total power consumption of 84 μW. For low rate
applications the decoder consumes only 47 μW at a throughput of 250
kb/s.

Original language	English
Title of host publication	[Host publication title missing]
Pages	2881-2884
DOIs	https://doi.org/10.1109/ISCAS.2011.5938233
Publication status	Published - 2011
Event	IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 - Rio de Janeiro, Rio de Janeiro, Brazil Duration: 2011 May 15 → 2011 May 18

Publication series

Name
ISSN (Print)	2158-1525
ISSN (Electronic)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	2011/05/15 → 2011/05/18

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/ISCAS.2011.5938233

Cite this

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title = "An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications",

abstract = "A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s.",

author = "Reza Meraji and Anderson, \{John B\} and Henrik Sj{\"o}land and Viktor {\"O}wall",

year = "2011",

doi = "10.1109/ISCAS.2011.5938233",

language = "English",

isbn = "978-1-4244-9473-6",

pages = "2881--2884",

booktitle = "[Host publication title missing]",

note = "IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

TY - GEN

T1 - An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

AU - Meraji, Reza

AU - Anderson, John B

AU - Sjöland, Henrik

AU - Öwall, Viktor

PY - 2011

Y1 - 2011

N2 - A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s.

AB - A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s.

UR - https://www.scopus.com/pages/publications/79960881619

U2 - 10.1109/ISCAS.2011.5938233

DO - 10.1109/ISCAS.2011.5938233

M3 - Paper in conference proceeding

SN - 978-1-4244-9473-6

SP - 2881

EP - 2884

BT - [Host publication title missing]

T2 - IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011

Y2 - 15 May 2011 through 18 May 2011

ER -

An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

Abstract

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