This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> for a <inline-formula> <tex-math notation="LaTeX">$128\times 8$</tex-math> </inline-formula> massive MIMO system.

Original languageEnglish
Pages (from-to)1-12
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Publication statusPublished - 2022

Subject classification (UKÄ)

  • Computer Engineering

Free keywords

  • 5G
  • accelerator architecture
  • ASIP
  • Baseband
  • baseband processor
  • communications processor
  • Complexity theory
  • Computer architecture
  • computer architecture
  • Massive MIMO
  • massive MIMO
  • Mathematical models
  • Matrix decomposition
  • matrix processor
  • parallel memory
  • Precoding
  • programmable processor
  • SIMD
  • systolic arrays
  • vector processor
  • VLIW


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