An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level

Masoud Nouripayam; Arturo Prieto; Vignajeth Kuttuva Kishorelal; Joachim Rodrigues

doi:10.1109/ICECS53924.2021.9665530

An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level

Masoud Nouripayam, Arturo Prieto, Vignajeth Kuttuva Kishorelal, Joachim Rodrigues

Lund University

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.

Original language	English
Title of host publication	2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
ISBN (Electronic)	978-1-7281-8281-0
ISBN (Print)	978-1-7281-9493-6
DOIs	https://doi.org/10.1109/ICECS53924.2021.9665530
Publication status	Published - 2021 Dec

Subject classification (UKÄ)

Computer Engineering
Computer Systems

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICECS53924.2021.9665530

Cite this

Nouripayam, M., Prieto, A., Kishorelal, V. K., & Rodrigues, J. (2021). An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level. In 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (pp. 1-4). IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS53924.2021.9665530

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title = "An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level",

abstract = "A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.",

author = "Masoud Nouripayam and Arturo Prieto and Kishorelal, {Vignajeth Kuttuva} and Joachim Rodrigues",

year = "2021",

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doi = "10.1109/ICECS53924.2021.9665530",

language = "English",

isbn = "978-1-7281-9493-6",

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An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level. / Nouripayam, Masoud ; Prieto, Arturo; Kishorelal, Vignajeth Kuttuva et al.
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2021. p. 1-4.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level

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AU - Kishorelal, Vignajeth Kuttuva

AU - Rodrigues, Joachim

PY - 2021/12

Y1 - 2021/12

N2 - A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.

AB - A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.

U2 - 10.1109/ICECS53924.2021.9665530

DO - 10.1109/ICECS53924.2021.9665530

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BT - 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

ER -

An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level

Abstract

Subject classification (UKÄ)

UN SDGs

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