Abstract
in today’s technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.
| Original language | English |
|---|---|
| Title of host publication | 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 |
| Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| Pages | 717-720 |
| ISBN (Print) | 978-1-4244-2341-5 |
| Publication status | Published - 2008 |
| Event | The 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008) - Macao, China Duration: 2008 Nov 30 → 2008 Dec 3 |
Conference
| Conference | The 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008) |
|---|---|
| Country/Territory | China |
| City | Macao |
| Period | 2008/11/30 → 2008/12/03 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering