ASIC Implementation of a Delayless Acoustic Echo Canceller: Architecture and Arithmetic

Application specific digital signal processors are superior compared to standard digital signal processors in a number of application fields, mainly due to high throughput and low power consumption traded for flexibility. This thesis deals with two areas related to hardware implementation of custom digital signal processors: design methodology and efficient implementation of arithmetic circuits. A delayless acoustic echo canceller is chosen as an example algorithm for custom hardware implementation. The canceller algorithm with no signal path delay is suitable in telecommunication applications, and has a high implementation complexity both in number of operations per second and in the variety of signal processing elements it is composed of. The design methodology developed and applied during the echo canceller hardware implementation is presented together with a number of optimizations applicable to the algorithm, architecture, and arithmetic design levels. The work on digital arithmetic circuits includes efficient implementation of dividers and complex multipliers. A configurable divider architecture for use in a wide range of applications is proposed. The divider is based on digit recurrence algorithms. A parameterized complex multiplier designed for low power consumption and high throughput applications is presented. The multiplier is based on distributed arithmetic, offset binary coding, and adder trees. Furthermore, an arithmetic co-optimization between two algorithms, the fast Fourier transform and the FIR filter, is proposed. The acoustic echo canceller chip has been fabricated and verified for functionality, throughput, and power consumption.