Balancing BlockRAM and distributed RAM

Wen Hai Fang; Thomas Johansson; Lambert Spaanenburg

Balancing BlockRAM and distributed RAM

Wen Hai Fang, Thomas Johansson, Lambert Spaanenburg

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

Original language	English
Title of host publication	Proceedings SSoCC 2005
Publication status	Published - 2005
Event	Swedish System-on-Chip Conference (SSoCC'05) - Tammsvik, Tammsvik, Sweden Duration: 2005 Apr 18 → 2005 Apr 19

Conference

Conference	Swedish System-on-Chip Conference (SSoCC'05)
Country/Territory	Sweden
City	Tammsvik
Period	2005/04/18 → 2005/04/19

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Cite this

@inproceedings{6984b24fcd574a56b11315b314dc60af,

title = "Balancing BlockRAM and distributed RAM",

abstract = "Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.",

author = "Fang, \{Wen Hai\} and Thomas Johansson and Lambert Spaanenburg",

year = "2005",

language = "English",

booktitle = "Proceedings SSoCC 2005",

note = "Swedish System-on-Chip Conference (SSoCC'05) ; Conference date: 18-04-2005 Through 19-04-2005",

}

TY - GEN

T1 - Balancing BlockRAM and distributed RAM

AU - Fang, Wen Hai

AU - Johansson, Thomas

AU - Spaanenburg, Lambert

PY - 2005

Y1 - 2005

N2 - Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

AB - Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

M3 - Paper in conference proceeding

BT - Proceedings SSoCC 2005

T2 - Swedish System-on-Chip Conference (SSoCC'05)

Y2 - 18 April 2005 through 19 April 2005

ER -

Balancing BlockRAM and distributed RAM

Abstract

Conference

Subject classification (UKÄ)

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Cite this