Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method

Sofia Johansson, Jiongjiong Mo, Erik Lind

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.
Original languageEnglish
Title of host publication2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages53-56
Publication statusPublished - 2013
Event43rd Conference on European Solid-State Device Research - Bucharest, ROMANIA
Duration: 2013 Sept 162013 Sept 20

Publication series

Name
ISSN (Print)1930-8876

Conference

Conference43rd Conference on European Solid-State Device Research
Period2013/09/162013/09/20

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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