Abstract
This paper presents class-D CMOS oscillators capable of an excellent phase noise performance from a very low power supply voltage. Starting from the recognition of the time-variant nature of the class-D LC tank, accurate expressions of the oscillation frequency, oscillation amplitude, current consumption, phase noise, and figure-of-merit (FoM) have been derived. Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing. A prototype of a class-D voltage-controlled oscillator (VCO) targeted for mobile applications, implemented in a standard 65-nm CMOS process, covers a 46% tuning range between 3.0 and 4.8 GHz; drawing 10 mA from 0.4 V, the phase noise at 10-MHz offset from 4.8 GHz is -143.5 dBc/Hz, for an FoM of 191 dBc/Hz with less than 1-dB variation across the tuning range. A version of the same VCO with a resonant tail filter displays a lower 1/f(3) phase-noise corner and improves the FoM by 1 dB.
Original language | English |
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Pages (from-to) | 3105-3119 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 48 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2013 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- Class-D
- CMOS
- high efficiency
- low phase noise
- low-voltage
- voltage-controlled oscillator (VCO)