Combined scheduling and instruction selection for processors with reconfigurable cell fabric

Antoine Floch; Christophe Wolinski; Krzysztof Kuchcinski

doi:10.1109/ASAP.2010.5540997

Combined scheduling and instruction selection for processors with reconfigurable cell fabric

Antoine Floch, Christophe Wolinski, Krzysztof Kuchcinski

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.

Original language	English
Title of host publication	21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	167-174
ISBN (Print)	978-1-4244-6966-6
DOIs	https://doi.org/10.1109/ASAP.2010.5540997
Publication status	Published - 2010
Event	21st IEEE International Conference on Application-specific Systems, Architectures and Processors - Rennes, France Duration: 2010 Jul 7 → 2010 Jul 9

Publication series

Name
ISSN (Print)	2160-0511

Conference

Conference	21st IEEE International Conference on Application-specific Systems, Architectures and Processors
Country/Territory	France
City	Rennes
Period	2010/07/07 → 2010/07/09

Subject classification (UKÄ)

Computer Sciences

Access to Document

10.1109/ASAP.2010.5540997

EASE: Embedded Applications Software Engineering
Åkesson, J. (Researcher), Magnusson, B. (Researcher), Svensson Fors, D. (Researcher), Magnusson, E. (Researcher), Hedin, G. (Researcher), Kuchcinski, K. (Researcher), Andersson, P. (Researcher), Nugues, P. (Researcher), Robertz, S. (Researcher), Ekman, T. (Researcher), Loconsole, A. (Researcher), Orucevic-Alagic, A. (Researcher), Johnsson, B. A. (Researcher), Pfahl, D. (Researcher), Bjarnason, E. (Researcher), Söderberg, E. (Researcher), Sabaliauskaité, G. (Researcher), Jonsson, H. (Researcher), Janneck, J. (Researcher), Wnuk, K. (Researcher), Borg, M. (Researcher), Skoglund, M. (Researcher), Sulaman, S. M. (Researcher), Minör, S. (Researcher), Sandholm, T. (Researcher), Alce, G. (Researcher), Wallergård, M. (Researcher), Zhang, C. (Researcher), Barney, S. (Researcher), Martinsen, J. K. (Researcher), Grahn, H. (Researcher), Jalali, S. (Researcher), Ardö, A. (Researcher), Engström, E. (Researcher), Berntsson Svensson, R. (Researcher), Regnell, B. (Researcher), Runeson, P. (PI), Wohlin, C. (PI), Höst, M. (Researcher) & Wisbrant, J. (Project communication officer)
2008/09/30 → 2018/12/31
Project: Research

Cite this

Floch, A., Wolinski, C., & Kuchcinski, K. (2010). Combined scheduling and instruction selection for processors with reconfigurable cell fabric. In 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010 (pp. 167-174). IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2010.5540997

@inproceedings{84a28b2e5eeb4a9e9d69f1cfee6bbb79,

title = "Combined scheduling and instruction selection for processors with reconfigurable cell fabric",

abstract = "This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.",

author = "Antoine Floch and Christophe Wolinski and Krzysztof Kuchcinski",

year = "2010",

doi = "10.1109/ASAP.2010.5540997",

language = "English",

isbn = "978-1-4244-6966-6",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "167--174",

booktitle = "21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010",

address = "United States",

note = "21st IEEE International Conference on Application-specific Systems, Architectures and Processors ; Conference date: 07-07-2010 Through 09-07-2010",

}

Floch, A, Wolinski, C & Kuchcinski, K 2010, Combined scheduling and instruction selection for processors with reconfigurable cell fabric. in 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 167-174, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, Rennes, France, 2010/07/07. https://doi.org/10.1109/ASAP.2010.5540997

Combined scheduling and instruction selection for processors with reconfigurable cell fabric. / Floch, Antoine; Wolinski, Christophe; Kuchcinski, Krzysztof.
21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010. IEEE - Institute of Electrical and Electronics Engineers Inc., 2010. p. 167-174.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Combined scheduling and instruction selection for processors with reconfigurable cell fabric

AU - Floch, Antoine

AU - Wolinski, Christophe

AU - Kuchcinski, Krzysztof

PY - 2010

Y1 - 2010

N2 - This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.

AB - This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.

U2 - 10.1109/ASAP.2010.5540997

DO - 10.1109/ASAP.2010.5540997

M3 - Paper in conference proceeding

SN - 978-1-4244-6966-6

SP - 167

EP - 174

BT - 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors

Y2 - 7 July 2010 through 9 July 2010

ER -

Combined scheduling and instruction selection for processors with reconfigurable cell fabric

Abstract

Publication series

Conference

Subject classification (UKÄ)

Access to Document

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Projects

EASE: Embedded Applications Software Engineering

Cite this