Complementary III-V heterojunction lateral NW Tunnel FET technology on Si

Davide Cutaia; Kirsten E. Moselund; Heinz Schmid; M. Borg; Antonis Olziersky; Heike Riel

doi:10.1109/VLSIT.2016.7573444

Complementary III-V heterojunction lateral NW Tunnel FET technology on Si

Davide Cutaia, Kirsten E. Moselund, Heinz Schmid, M. Borg, Antonis Olziersky, Heike Riel

NanoLund: Centre for Nanoscience

IBM Research Zurich

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SS_ave, of ∼70mV/dec. combined with an on-current, I_on, of 4μA/μm at V_DS = V_GS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher I_on, but SS is deteriorated due to high interface traps density (D_it).

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Volume	2016-September
ISBN (Electronic)	9781509006373
DOIs	https://doi.org/10.1109/VLSIT.2016.7573444
Publication status	Published - 2016 Sept 21
Event	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States Duration: 2016 Jun 13 → 2016 Jun 16

Conference

Conference	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/Territory	United States
City	Honolulu
Period	2016/06/13 → 2016/06/16

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/VLSIT.2016.7573444

Cite this

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title = "Complementary III-V heterojunction lateral NW Tunnel FET technology on Si",

abstract = "We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).",

author = "Davide Cutaia and Moselund, {Kirsten E.} and Heinz Schmid and M. Borg and Antonis Olziersky and Heike Riel",

year = "2016",

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doi = "10.1109/VLSIT.2016.7573444",

language = "English",

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booktitle = "2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016",

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note = "36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",

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Cutaia, D, Moselund, KE, Schmid, H, Borg, M, Olziersky, A & Riel, H 2016, Complementary III-V heterojunction lateral NW Tunnel FET technology on Si. in 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. vol. 2016-September, 7573444, IEEE - Institute of Electrical and Electronics Engineers Inc., 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 2016/06/13. https://doi.org/10.1109/VLSIT.2016.7573444

Complementary III-V heterojunction lateral NW Tunnel FET technology on Si. / Cutaia, Davide; Moselund, Kirsten E.; Schmid, Heinz et al.
2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Vol. 2016-September IEEE - Institute of Electrical and Electronics Engineers Inc., 2016. 7573444.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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T1 - Complementary III-V heterojunction lateral NW Tunnel FET technology on Si

AU - Cutaia, Davide

AU - Moselund, Kirsten E.

AU - Schmid, Heinz

AU - Borg, M.

AU - Olziersky, Antonis

AU - Riel, Heike

PY - 2016/9/21

Y1 - 2016/9/21

N2 - We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).

AB - We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).

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DO - 10.1109/VLSIT.2016.7573444

M3 - Paper in conference proceeding

AN - SCOPUS:84991011686

VL - 2016-September

BT - 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016

Y2 - 13 June 2016 through 16 June 2016

ER -

Complementary III-V heterojunction lateral NW Tunnel FET technology on Si

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