Compressor design for silicon debug

Jing Zhang; Lars Johan Fritz; Liang Liu; Erik Larsson

doi:10.1109/ETS.2016.7519281

Compressor design for silicon debug

Jing Zhang, Lars Johan Fritz, Liang Liu, Erik Larsson

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.

Original language	English
Title of host publication	Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467396592
DOIs	https://doi.org/10.1109/ETS.2016.7519281
Publication status	Published - 2016 Jul 22
Event	21st IEEE European Test Symposium, ETS 2016 - Amsterdam, Netherlands Duration: 2016 May 23 → 2016 May 26

Conference

Conference	21st IEEE European Test Symposium, ETS 2016
Country/Territory	Netherlands
City	Amsterdam
Period	2016/05/23 → 2016/05/26

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/ETS.2016.7519281

Cite this

@inproceedings{0f3114ad040641088a46a4ec4545bffa,

title = "Compressor design for silicon debug",

abstract = "The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.",

author = "Jing Zhang and Fritz, {Lars Johan} and Liang Liu and Erik Larsson",

year = "2016",

month = jul,

day = "22",

doi = "10.1109/ETS.2016.7519281",

language = "English",

booktitle = "Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "21st IEEE European Test Symposium, ETS 2016 ; Conference date: 23-05-2016 Through 26-05-2016",

}

TY - GEN

T1 - Compressor design for silicon debug

AU - Zhang, Jing

AU - Fritz, Lars Johan

AU - Liu, Liang

AU - Larsson, Erik

PY - 2016/7/22

Y1 - 2016/7/22

N2 - The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.

AB - The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.

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U2 - 10.1109/ETS.2016.7519281

DO - 10.1109/ETS.2016.7519281

M3 - Paper in conference proceeding

AN - SCOPUS:84991492520

BT - Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE European Test Symposium, ETS 2016

Y2 - 23 May 2016 through 26 May 2016

ER -

Compressor design for silicon debug

Abstract

Conference

Subject classification (UKÄ)

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