Core-shell tfet developments and tfet limitations

Tunneling field-effect transistors (TFET) based on a vertical gate-All-Around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current \mathrm{I}-{\mathrm{o}\mathrm{n}} of 6.7\ \mu \mathrm{A} (NW diameter \mathrm{d}= 10.2\ \mathrm{nm}) at \mathrm{V}-{\mathrm{dd}}=0.3\ \mathrm{V} under low power (LP) conditions (\mathrm{I}-{\mathrm{off}}=1 \mathrm{pA}) for an InAs/GaSb CS TFET. This compares to Si nMOSFET \mathrm{I}-{\mathrm{on}} =2.3\ \mu \mathrm{A} at \mathrm{V}-{\mathrm{dd}}=0.55\ \mathrm{V}(\mathrm{d}=6\ \mathrm{nm}). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of \mathrm{d}-{\mathrm{c}}= 17 nm (GaSb core) and \mathrm{t}-{\mathrm{sh}}=3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40\ \mu \mathrm{A} (\mathrm{V}-{\mathrm{d}}=0.3\ \mathrm{V}) and subthreshold swing \mathrm{SS}=40\mathrm{mV}/\mathrm{dec}(\mathrm{V}-{\mathrm{d}}=10\mathrm{mV}) for NW diameters between 35-50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-To band-Tunneling (BTBT) and \mathrm{D}-{\mathrm{it}} related trap assisted tunneling (TAT) was found which imposes challenging \mathrm{D}-{\mathrm{it}} requirements, in particular for LP \mathrm{I}-{\mathrm{off}} specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.