Design and implementation of a 1024-point pipeline FFT processor

Shousheng He; Mats Torkelson

doi:10.1109/CICC.1998.694922

Design and implementation of a 1024-point pipeline FFT processor

Shousheng He, Mats Torkelson

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.

Original language	English
Title of host publication	[Host publication title missing]
Pages	131-134
DOIs	https://doi.org/10.1109/CICC.1998.694922
Publication status	Published - 1998
Event	The IEEE Custom Integrated Circuits Conference, 1998 - Santa Clara, CA, United States Duration: 1998 May 11 → 1998 May 14

Conference

Conference	The IEEE Custom Integrated Circuits Conference, 1998
Country/Territory	United States
City	Santa Clara, CA
Period	1998/05/11 → 1998/05/14

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

CMOS digital integrated circuits
VLSI
digital signal processing chips
fast Fourier transforms
pipeline processing

Access to Document

10.1109/CICC.1998.694922

Cite this

@inproceedings{a1c9dd7ec3bd4875aeac4369d3df4ac9,

title = "Design and implementation of a 1024-point pipeline FFT processor",

abstract = "The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.",

keywords = "CMOS digital integrated circuits, VLSI, digital signal processing chips, fast Fourier transforms, pipeline processing",

author = "Shousheng He and Mats Torkelson",

year = "1998",

doi = "10.1109/CICC.1998.694922",

language = "English",

isbn = "0-7803-4292-5",

pages = "131--134",

booktitle = "[Host publication title missing]",

note = "The IEEE Custom Integrated Circuits Conference, 1998 ; Conference date: 11-05-1998 Through 14-05-1998",

}

TY - GEN

T1 - Design and implementation of a 1024-point pipeline FFT processor

AU - He, Shousheng

AU - Torkelson, Mats

PY - 1998

Y1 - 1998

N2 - The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.

AB - The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.

KW - CMOS digital integrated circuits

KW - VLSI

KW - digital signal processing chips

KW - fast Fourier transforms

KW - pipeline processing

U2 - 10.1109/CICC.1998.694922

DO - 10.1109/CICC.1998.694922

M3 - Paper in conference proceeding

SN - 0-7803-4292-5

SP - 131

EP - 134

BT - [Host publication title missing]

T2 - The IEEE Custom Integrated Circuits Conference, 1998

Y2 - 11 May 1998 through 14 May 1998

ER -

Design and implementation of a 1024-point pipeline FFT processor

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Cite this