Design considerations of a floating-point ADC with embedded S/H

Johan Piper, Jiren Yuan

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingResearchpeer-review

7 Citations (SciVal)

Abstract

This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages6166-6169
ISBN (Print)0-7803-8834-8
DOIs
Publication statusPublished - 2005
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2005
Country/TerritoryJapan
CityKobe
Period2005/05/232005/05/26

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • resistive weighting
  • chopped gain stages
  • input referred thermal noise
  • channel matching
  • ADC distortion
  • settling time
  • delay
  • floating-point ADC
  • embedded S/H
  • offset matching
  • robust channel selecting logic

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