Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Syed Muhammad Yasser Sherazi; Peter Nilsson; OmerCan Akgun; Henrik Sjöland; Joachim Rodrigues

doi:10.1109/ISCAS.2011.5937696

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Syed Muhammad Yasser Sherazi, Peter Nilsson, OmerCan Akgun, Henrik Sjöland, Joachim Rodrigues

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents an analysis on energy dissipation
of digital half-band filters operating in the sub-threshold
(sub-VT) region with throughput and supply voltage constraints.
A 12-bit filter is implemented along with various unfolded
structures, used to form a decimation filter chain. The designs
are synthesized in a 65 nm low-leakage CMOS technology with
various threshold voltages. A sub-VT energy model is applied to
characterize the designs in the sub-VT domain. The results show
that the low-leakage standard-threshold technology is suitable
for the required throughput range between 250Ksamples/s and
2Msamples/s, at a supply voltage of 260mV. The total energy
dissipation of the filter is 205 fJ per sample.

Original language	English
Title of host publication	2011 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	837-840
DOIs	https://doi.org/10.1109/ISCAS.2011.5937696
Publication status	Published - 2011
Event	IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 - Rio de Janeiro, Rio de Janeiro, Brazil Duration: 2011 May 15 → 2011 May 18

Publication series

Name
ISSN (Print)	0271-4310
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	2011/05/15 → 2011/05/18

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

CMOS
sub-threshold
65 nm
Sub-VT
Chain
low power
Ultra Low energy
Decimation Filter
Digital

Access to Document

10.1109/ISCAS.2011.5937696

Cite this

@inproceedings{78afead60af34977bf071e2fcdff8fbe,

title = "Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain",

abstract = "This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250Ksamples/s and 2Msamples/s, at a supply voltage of 260mV. The total energy dissipation of the filter is 205 fJ per sample.",

keywords = "CMOS, sub-threshold, 65 nm, Sub-VT, Chain, low power, Ultra Low energy, Decimation Filter, Digital",

author = "Sherazi, {Syed Muhammad Yasser} and Peter Nilsson and OmerCan Akgun and Henrik Sj{\"o}land and Joachim Rodrigues",

year = "2011",

doi = "10.1109/ISCAS.2011.5937696",

language = "English",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "837--840",

booktitle = "2011 IEEE International Symposium on Circuits and Systems (ISCAS)",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

Sherazi, SMY, Nilsson, P, Akgun, O, Sjöland, H & Rodrigues, J 2011, Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. in 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 837-840, IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011, Rio de Janeiro, Brazil, 2011/05/15. https://doi.org/10.1109/ISCAS.2011.5937696

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. / Sherazi, Syed Muhammad Yasser; Nilsson, Peter; Akgun, OmerCan et al.
2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2011. p. 837-840.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

AU - Sherazi, Syed Muhammad Yasser

AU - Nilsson, Peter

AU - Akgun, OmerCan

AU - Sjöland, Henrik

AU - Rodrigues, Joachim

PY - 2011

Y1 - 2011

N2 - This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250Ksamples/s and 2Msamples/s, at a supply voltage of 260mV. The total energy dissipation of the filter is 205 fJ per sample.

AB - This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250Ksamples/s and 2Msamples/s, at a supply voltage of 260mV. The total energy dissipation of the filter is 205 fJ per sample.

KW - CMOS

KW - sub-threshold

KW - 65 nm

KW - Sub-VT

KW - Chain

KW - low power

KW - Ultra Low energy

KW - Decimation Filter

KW - Digital

U2 - 10.1109/ISCAS.2011.5937696

DO - 10.1109/ISCAS.2011.5937696

M3 - Paper in conference proceeding

SP - 837

EP - 840

BT - 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011

Y2 - 15 May 2011 through 18 May 2011

ER -

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Abstract

Publication series

Conference

Subject classification (UKÄ)

Free keywords

Access to Document

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Cite this