Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Chenxin Zhang; Thomas Lenart; Henrik Svensson; Viktor Öwall

doi:10.1109/ReConFig.2009.49

Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.

Original language	English
Title of host publication	International Conference on Reconfigurable Computing and FPGAs
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	338-343
Number of pages	6
ISBN (Print)	978-0-7695-3917-1
DOIs	https://doi.org/10.1109/ReConFig.2009.49
Publication status	Published - 2009
Event	2009 International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico Duration: 2009 Dec 9 → 2009 Dec 11

Conference

Conference	2009 International Conference on ReConFigurable Computing and FPGAs
Country/Territory	Mexico
City	Cancun
Period	2009/12/09 → 2009/12/11

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Coarse-grained reconfigurable architecture
FFT.
Dynamically reconfigurable cell array
Hybrid interconnect

Access to Document

10.1109/ReConFig.2009.49

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5382079&matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D(Design+of+coarse-grained+dynamically+reconfigurable+architecture+for+DSP+applications)

Cite this

@inproceedings{89e4fd19b7604e3686c079f33c4606ee,

title = "Design of coarse-grained dynamically reconfigurable architecture for DSP applications",

abstract = "This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.",

keywords = "Coarse-grained reconfigurable architecture, FFT., Dynamically reconfigurable cell array, Hybrid interconnect",

author = "Chenxin Zhang and Thomas Lenart and Henrik Svensson and Viktor {\"O}wall",

year = "2009",

doi = "10.1109/ReConFig.2009.49",

language = "English",

isbn = "978-0-7695-3917-1",

pages = "338--343",

booktitle = "International Conference on Reconfigurable Computing and FPGAs",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2009 International Conference on ReConFigurable Computing and FPGAs ; Conference date: 09-12-2009 Through 11-12-2009",

}

Zhang, C, Lenart, T, Svensson, H & Öwall, V 2009, Design of coarse-grained dynamically reconfigurable architecture for DSP applications. in International Conference on Reconfigurable Computing and FPGAs. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 338-343, 2009 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 2009/12/09. https://doi.org/10.1109/ReConFig.2009.49

Design of coarse-grained dynamically reconfigurable architecture for DSP applications. / Zhang, Chenxin; Lenart, Thomas; Svensson, Henrik et al.
International Conference on Reconfigurable Computing and FPGAs. IEEE - Institute of Electrical and Electronics Engineers Inc., 2009. p. 338-343.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Design of coarse-grained dynamically reconfigurable architecture for DSP applications

AU - Zhang, Chenxin

AU - Lenart, Thomas

AU - Svensson, Henrik

AU - Öwall, Viktor

PY - 2009

Y1 - 2009

N2 - This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.

AB - This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.

KW - Coarse-grained reconfigurable architecture

KW - FFT.

KW - Dynamically reconfigurable cell array

KW - Hybrid interconnect

U2 - 10.1109/ReConFig.2009.49

DO - 10.1109/ReConFig.2009.49

M3 - Paper in conference proceeding

SN - 978-0-7695-3917-1

SP - 338

EP - 343

BT - International Conference on Reconfigurable Computing and FPGAs

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2009 International Conference on ReConFigurable Computing and FPGAs

Y2 - 9 December 2009 through 11 December 2009

ER -

Design of coarse-grained dynamically reconfigurable architecture for DSP applications

Abstract

Conference

Subject classification (UKÄ)

Free keywords

Access to Document

Fingerprint

Cite this