Design of Reconfigurable Hardware Architectures for Real-time Applications

This thesis discusses modeling and implementation of reconfigurable hardware
architectures for real-time applications. The target application in this work
is digital holographic imaging, where visible images are to be reconstructed
based on holographic recordings. The reconstruction process is computationally
demanding and requires hardware acceleration to achieve real-time performance.
Thus, this work presents two design approaches, with different levels
of reconfigurability, to accelerate the image reconstruction process and related
computationally demanding applications.

The first approach is based on application-specific hardware accelerators, which
are usually required in systems with high constraints on processing performance,
physical size, or power consumption, and are tailored for a certain
application to achieve high performance. Hence, an acceleration platform
is proposed and designed to enable real-time image reconstruction in digital
holographic imaging, constituting a set of hardware accelerators that are connected
in a flexible and reconfigurable pipeline. Hardware accelerators are
optimized for high computational performance and low memory requirements.
The application-specific design has been integrated into an embedded system
consisting of a microprocessor, a high-performance memory controller, a digital
image sensor, and a video output device. The system has been prototyped
using an FPGA platform and synthesized for a 0.13 μm standard cell library,
achieving a reconstruction rate of 30 frames per second running at 400 MHz.

The second approach is based on a dynamically reconfigurable architecture
to accelerate arbitrary applications, which presents a trade-off between versatileness
and hardware cost. The proposed reconfigurable architecture is constructed
from processing and memory cells, which communicate using a combination
of local interconnects and a global network. High-performance local
interconnects generate a high communication bandwidth between neighboring
cells, while the global network provides flexibility and access to external memory.
The processing and memory cells are run-time reconfigurable to enable
flexible application mapping. Proposed reconfigurable architectures are modeled
and evaluated using Scenic, which is a system-level exploration environment
developed in this work. A design with 16 cells is implemented and synthesized
for a 0.13 μm standard cell library, resulting in low area overhead when
compared with application-specific solutions. It is shown that the proposed
reconfigurable architecture achieves high computation performance compared
to traditional DSP processors.