Design of RF Properties for Vertical Nanowire MOSFETs

The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.