Abstract
Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal
Original language | English |
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Pages (from-to) | 1311-1313 |
Journal | Electronics Letters |
Volume | 24 |
Issue number | 21 |
Publication status | Published - 1988 |
Externally published | Yes |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering