FPGA based hybrid computing platform for ESS linac simulator

Arun Jeevaraj; Emmanuel Laface; Maurizio Donna; Fredrik Edman; Liang Liu

doi:10.1109/NORCHIP.2018.8573518

FPGA based hybrid computing platform for ESS linac simulator

Arun Jeevaraj, Emmanuel Laface, Maurizio Donna, Fredrik Edman, Liang Liu

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a scalable and high-Throughput hybrid computing platform for the real-Time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 10¹² matrix multiplication operations for a test case of 10⁶ beam particles simulated over 10⁶ cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU-and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to 89 × speed up compared to a C++ benchmark of the same system.

Original language	English
Title of host publication	2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018
Subtitle of host publication	NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings
Editors	Jari Nurmi, Peeter Ellervee, Juri Mihhailov, Kalle Tammemae, Maksim Jenihhin
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676561
DOIs	https://doi.org/10.1109/NORCHIP.2018.8573518
Publication status	Published - 2018 Dec 11
Event	4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Tallinn, Estonia Duration: 2018 Oct 30 → 2018 Oct 31

Conference

Conference	4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018
Country/Territory	Estonia
City	Tallinn
Period	2018/10/30 → 2018/10/31

Subject classification (UKÄ)

Computer Sciences

Access to Document

10.1109/NORCHIP.2018.8573518

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Jeevaraj, A., Laface, E., Donna, M., Edman, F., & Liu, L. (2018). FPGA based hybrid computing platform for ESS linac simulator. In J. Nurmi, P. Ellervee, J. Mihhailov, K. Tammemae, & M. Jenihhin (Eds.), 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings Article 8573518 IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NORCHIP.2018.8573518

Jeevaraj, Arun ; Laface, Emmanuel ; Donna, Maurizio et al. / FPGA based hybrid computing platform for ESS linac simulator. 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. editor / Jari Nurmi ; Peeter Ellervee ; Juri Mihhailov ; Kalle Tammemae ; Maksim Jenihhin. IEEE - Institute of Electrical and Electronics Engineers Inc., 2018.

@inproceedings{0dec190cbb4648c3afb0365766c99645,

title = "FPGA based hybrid computing platform for ESS linac simulator",

abstract = "This paper presents a scalable and high-Throughput hybrid computing platform for the real-Time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 1012 matrix multiplication operations for a test case of 106 beam particles simulated over 106 cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU-and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to 89 × speed up compared to a C++ benchmark of the same system.",

author = "Arun Jeevaraj and Emmanuel Laface and Maurizio Donna and Fredrik Edman and Liang Liu",

year = "2018",

month = dec,

day = "11",

doi = "10.1109/NORCHIP.2018.8573518",

language = "English",

editor = "Jari Nurmi and Peeter Ellervee and Juri Mihhailov and Kalle Tammemae and Maksim Jenihhin",

booktitle = "2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 ; Conference date: 30-10-2018 Through 31-10-2018",

}

Jeevaraj, A, Laface, E, Donna, M, Edman, F & Liu, L 2018, FPGA based hybrid computing platform for ESS linac simulator. in J Nurmi, P Ellervee, J Mihhailov, K Tammemae & M Jenihhin (eds), 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings., 8573518, IEEE - Institute of Electrical and Electronics Engineers Inc., 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018, Tallinn, Estonia, 2018/10/30. https://doi.org/10.1109/NORCHIP.2018.8573518

FPGA based hybrid computing platform for ESS linac simulator. / Jeevaraj, Arun; Laface, Emmanuel; Donna, Maurizio et al.
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. ed. / Jari Nurmi; Peeter Ellervee; Juri Mihhailov; Kalle Tammemae; Maksim Jenihhin. IEEE - Institute of Electrical and Electronics Engineers Inc., 2018. 8573518.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - FPGA based hybrid computing platform for ESS linac simulator

AU - Jeevaraj, Arun

AU - Laface, Emmanuel

AU - Donna, Maurizio

AU - Edman, Fredrik

AU - Liu, Liang

PY - 2018/12/11

Y1 - 2018/12/11

N2 - This paper presents a scalable and high-Throughput hybrid computing platform for the real-Time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 1012 matrix multiplication operations for a test case of 106 beam particles simulated over 106 cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU-and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to 89 × speed up compared to a C++ benchmark of the same system.

AB - This paper presents a scalable and high-Throughput hybrid computing platform for the real-Time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 1012 matrix multiplication operations for a test case of 106 beam particles simulated over 106 cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU-and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to 89 × speed up compared to a C++ benchmark of the same system.

U2 - 10.1109/NORCHIP.2018.8573518

DO - 10.1109/NORCHIP.2018.8573518

M3 - Paper in conference proceeding

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BT - 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018

A2 - Nurmi, Jari

A2 - Ellervee, Peeter

A2 - Mihhailov, Juri

A2 - Tammemae, Kalle

A2 - Jenihhin, Maksim

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018

Y2 - 30 October 2018 through 31 October 2018

ER -

Jeevaraj A, Laface E, Donna M, Edman F , Liu L. FPGA based hybrid computing platform for ESS linac simulator. In Nurmi J, Ellervee P, Mihhailov J, Tammemae K, Jenihhin M, editors, 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc. 2018. 8573518 doi: 10.1109/NORCHIP.2018.8573518

FPGA based hybrid computing platform for ESS linac simulator

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