FPGA implementation of controller-datapath pair in custom image processor design

Hongtu Jiang, Viktor Öwall

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency.
Original languageEnglish
Title of host publicationProceedings of the 2004 International Symposium on Circuits and Systems
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages141-144
Volume5
Publication statusPublished - 2004
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2004 - Vancouver, BC, Canada
Duration: 2004 May 232004 May 26

Publication series

Name
Volume5
ISSN (Print)0271-4310
ISSN (Electronic)2158-1525

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2004
Country/TerritoryCanada
CityVancouver, BC
Period2004/05/232004/05/26

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • Line memories
  • Image processors
  • Clock cycles
  • Image size

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