Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Deepak Dasalukunte; Karthik Ananthanarayanan; Murali Kandasamy; Fredrik Rusek; Viktor Öwall

doi:10.1109/NORCHP.2009.5397801

Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Deepak Dasalukunte, Karthik Ananthanarayanan, Murali Kandasamy, Fredrik Rusek, Viktor Öwall

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory
(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes
prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II
Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.

Original language	English
Title of host publication	[Host publication title missing]
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	978-1-4244-4310-9
DOIs	https://doi.org/10.1109/NORCHP.2009.5397801
Publication status	Published - 2009
Event	Norchip Conference, 2009 - Trondheim, Norway Duration: 2009 Nov 16 → 2009 Nov 17 Conference number: 27

Conference

Conference	Norchip Conference, 2009
Country/Territory	Norway
City	Trondheim
Period	2009/11/16 → 2009/11/17

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

hardware implementation
faster-than-Nyquist
multicarrier
transmitter

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10.1109/NORCHP.2009.5397801

Cite this

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title = "Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter",

abstract = "This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.",

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author = "Deepak Dasalukunte and Karthik Ananthanarayanan and Murali Kandasamy and Fredrik Rusek and Viktor {\"O}wall",

year = "2009",

doi = "10.1109/NORCHP.2009.5397801",

language = "English",

isbn = "978-1-4244-4310-9",

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Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter. / Dasalukunte, Deepak; Ananthanarayanan, Karthik; Kandasamy, Murali et al.
[Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 2009.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

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AU - Ananthanarayanan, Karthik

AU - Kandasamy, Murali

AU - Rusek, Fredrik

AU - Öwall, Viktor

N1 - Conference code: 27

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N2 - This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.

AB - This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.

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KW - multicarrier

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DO - 10.1109/NORCHP.2009.5397801

M3 - Paper in conference proceeding

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BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - Norchip Conference, 2009

Y2 - 16 November 2009 through 17 November 2009

ER -

Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Abstract

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Subject classification (UKÄ)

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