Abstract
RF and DC characterization of vertical InAs nanowire MOSFET on Si substrates are presented. Nanowire arrays are epitaxially integrated on Si substrates by use of a thin InAs buffer layer. For device fabrication, high-k HfO2 gate dielectric and wrap-gates are used. Post-deposition annealing of the high-k is evaluated by comparing one annealed and one not-annealed sample. The annealed sample show better DC characteristics in terms of transconductance, g(m) = 155 mS/mm, and on-current, I-on = 550 mA/mm. Box plots of on-current, on-resistance and transconductance for all 190-nanowire-array transistors on the annealed sample suggest that the electrical properties of the nanowires are preserved when scaling the nanowire diameter. Finally, high frequency characterisation yields a unity current gain cut-off frequency of f(t) = 9.3 GHz for the annealed sample and f(t) = 2.0 GHz for the not-annealed sample. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Original language | English |
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Pages (from-to) | 350-353 |
Journal | Physica Status Solidi. C, Current Topics in Solid State Physics |
Volume | 9 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2012 |
Event | 38th International Symposium on Compound Semiconductors (ISCS)/23rd International Conference on Indium Phosphide and Related Materials (IPRM)/Compound Semiconductor Week - Berlin, Germany Duration: 2011 May 22 → 2011 May 26 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
- Condensed Matter Physics
Free keywords
- high-k
- annealing
- InAs
- high frequency
- nanowire
- MOSFET