Abstract
The IEEE Std. P1687.1 working group is currently exploring alternatives to IEEE Std. 1149.1 test access port (TAP) as the interface between the boundary of integrated circuits (ICs) and IEEE Std. 1687 networks. In this paper, we investigate the use of universal asynchronous receiver-transmitter (UART) to access IEEE Std. 1687 networks. We have developed a protocol to describe the information transported over UART and a hardware component to translate (retarget) information between UART and IEEE Std. 1687. The objective is to minimize the amount of information transported over UART and the area of the hardware component while maintaining the flexibility to access an arbitrary combination of instrument in the IEEE Std. 1687 network. We have developed software for the protocol translation, implemented the hardware component and IEEE Std. 1687 networks of different sizes in an field-programmable gate array (FPGA). For comparison, we developed a number of alternatives, all implemented on FPGA. The experimental results show that proposed scheme gives low overhead in terms of transported information (data) and low area of the hardware component.
Original language | English |
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Title of host publication | International Test Conference |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
DOIs | |
Publication status | Published - 2019 |
Event | International Test Conference (ITC) - Washington, United States Duration: 2019 Nov 12 → 2019 Nov 14 |
Conference
Conference | International Test Conference (ITC) |
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Country/Territory | United States |
City | Washington |
Period | 2019/11/12 → 2019/11/14 |
Subject classification (UKÄ)
- Other Electrical Engineering, Electronic Engineering, Information Engineering