III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon

Kirsten E. Moselund, Davide Cutaia, Heinz Schmid, M. Borg, Saurabh Sant, Andreas Schenk, Heike Riel

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = -0.5V, combined with average subthreshold swings (SS) of 70-80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The InAs/GaSb n-TFETs represent our first devices in this material system, with doping levels and gate stack not yet optimized; the all III-V TFETs show about an order of magnitude greater current levels, but at a worse SS.

Original languageEnglish
Title of host publicationNanotechnology Materials and Devices Conference, NMDC 2016 - Conference Proceedings
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509043521
DOIs
Publication statusPublished - 2016 Dec 7
Event11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016 - Toulouse, France
Duration: 2016 Oct 92016 Oct 12

Conference

Conference11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016
Country/TerritoryFrance
CityToulouse
Period2016/10/092016/10/12

Subject classification (UKÄ)

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

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