Implementation of an area efficient crypto processor for a NB-IoT SoC platform

Luis Cavo; Sebastien Fuhrmann; Liang Liu

doi:10.1109/NORCHIP.2018.8573517

Implementation of an area efficient crypto processor for a NB-IoT SoC platform

Luis Cavo, Sebastien Fuhrmann, Liang Liu

Lund University

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.

Original language	English
Title of host publication	2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018
Subtitle of host publication	NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings
Editors	Jari Nurmi, Peeter Ellervee, Juri Mihhailov, Kalle Tammemae, Maksim Jenihhin
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676561
DOIs	https://doi.org/10.1109/NORCHIP.2018.8573517
Publication status	Published - 2018 Dec 11
Event	4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Tallinn, Estonia Duration: 2018 Oct 30 → 2018 Oct 31

Conference

Conference	4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018
Country/Territory	Estonia
City	Tallinn
Period	2018/10/30 → 2018/10/31

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/NORCHIP.2018.8573517

Cite this

Cavo, L., Fuhrmann, S., & Liu, L. (2018). Implementation of an area efficient crypto processor for a NB-IoT SoC platform. In J. Nurmi, P. Ellervee, J. Mihhailov, K. Tammemae, & M. Jenihhin (Eds.), 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings Article 8573517 IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NORCHIP.2018.8573517

Cavo, Luis ; Fuhrmann, Sebastien ; Liu, Liang. / Implementation of an area efficient crypto processor for a NB-IoT SoC platform. 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. editor / Jari Nurmi ; Peeter Ellervee ; Juri Mihhailov ; Kalle Tammemae ; Maksim Jenihhin. IEEE - Institute of Electrical and Electronics Engineers Inc., 2018.

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title = "Implementation of an area efficient crypto processor for a NB-IoT SoC platform",

abstract = "This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.",

author = "Luis Cavo and Sebastien Fuhrmann and Liang Liu",

year = "2018",

month = dec,

day = "11",

doi = "10.1109/NORCHIP.2018.8573517",

language = "English",

editor = "Jari Nurmi and Peeter Ellervee and Juri Mihhailov and Kalle Tammemae and Maksim Jenihhin",

booktitle = "2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 ; Conference date: 30-10-2018 Through 31-10-2018",

}

Cavo, L, Fuhrmann, S & Liu, L 2018, Implementation of an area efficient crypto processor for a NB-IoT SoC platform. in J Nurmi, P Ellervee, J Mihhailov, K Tammemae & M Jenihhin (eds), 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings., 8573517, IEEE - Institute of Electrical and Electronics Engineers Inc., 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018, Tallinn, Estonia, 2018/10/30. https://doi.org/10.1109/NORCHIP.2018.8573517

Implementation of an area efficient crypto processor for a NB-IoT SoC platform. / Cavo, Luis; Fuhrmann, Sebastien; Liu, Liang.
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. ed. / Jari Nurmi; Peeter Ellervee; Juri Mihhailov; Kalle Tammemae; Maksim Jenihhin. IEEE - Institute of Electrical and Electronics Engineers Inc., 2018. 8573517.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Implementation of an area efficient crypto processor for a NB-IoT SoC platform

AU - Cavo, Luis

AU - Fuhrmann, Sebastien

AU - Liu, Liang

PY - 2018/12/11

Y1 - 2018/12/11

N2 - This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.

AB - This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.

U2 - 10.1109/NORCHIP.2018.8573517

DO - 10.1109/NORCHIP.2018.8573517

M3 - Paper in conference proceeding

AN - SCOPUS:85060600733

BT - 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018

A2 - Nurmi, Jari

A2 - Ellervee, Peeter

A2 - Mihhailov, Juri

A2 - Tammemae, Kalle

A2 - Jenihhin, Maksim

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018

Y2 - 30 October 2018 through 31 October 2018

ER -

Cavo L, Fuhrmann S, Liu L. Implementation of an area efficient crypto processor for a NB-IoT SoC platform. In Nurmi J, Ellervee P, Mihhailov J, Tammemae K, Jenihhin M, editors, 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc. 2018. 8573517 doi: 10.1109/NORCHIP.2018.8573517

Implementation of an area efficient crypto processor for a NB-IoT SoC platform

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