Implementation of an SVD Based MIMO OFDM channel estimator

Johan Löfgren; Shahid Mehmood; Nadir Khan; Babar Masood; M. Irfan Z. Awan; Imran Khan; Nafiz A. Chisty; Peter Nilsson

doi:10.1109/NORCHP.2009.5397840

Implementation of an SVD Based MIMO OFDM channel estimator

Johan Löfgren, Shahid Mehmood, Nadir Khan, Babar Masood, M. Irfan Z. Awan, Imran Khan, Nafiz A. Chisty, Peter Nilsson

Department of Electrical and Information Technology

Lund University

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.

Original language	English
Title of host publication	2009 NORCHIP
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	978-1-4244-4311-6
ISBN (Print)	9781424443109
DOIs	https://doi.org/10.1109/NORCHP.2009.5397840
Publication status	Published - 2010
Event	Norchip Conference, 2009 - Trondheim, Norway Duration: 2009 Nov 16 → 2009 Nov 17 Conference number: 27

Conference

Conference	Norchip Conference, 2009
Country/Territory	Norway
City	Trondheim
Period	2009/11/16 → 2009/11/17

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/NORCHP.2009.5397840

Cite this

@inproceedings{b13cca2e62f84b89b4b88d6623db7443,

title = "Implementation of an SVD Based MIMO OFDM channel estimator",

abstract = "This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.",

author = "Johan L{\"o}fgren and Shahid Mehmood and Nadir Khan and Babar Masood and Awan, {M. Irfan Z.} and Imran Khan and Chisty, {Nafiz A.} and Peter Nilsson",

year = "2010",

doi = "10.1109/NORCHP.2009.5397840",

language = "English",

isbn = "9781424443109",

booktitle = "2009 NORCHIP",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "Norchip Conference, 2009 ; Conference date: 16-11-2009 Through 17-11-2009",

}

TY - GEN

T1 - Implementation of an SVD Based MIMO OFDM channel estimator

AU - Löfgren, Johan

AU - Mehmood, Shahid

AU - Khan, Nadir

AU - Masood, Babar

AU - Awan, M. Irfan Z.

AU - Khan, Imran

AU - Chisty, Nafiz A.

AU - Nilsson, Peter

N1 - Conference code: 27

PY - 2010

Y1 - 2010

N2 - This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.

AB - This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.

U2 - 10.1109/NORCHP.2009.5397840

DO - 10.1109/NORCHP.2009.5397840

M3 - Paper in conference proceeding

SN - 9781424443109

BT - 2009 NORCHIP

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - Norchip Conference, 2009

Y2 - 16 November 2009 through 17 November 2009

ER -

Implementation of an SVD Based MIMO OFDM channel estimator

Abstract

Conference

Subject classification (UKÄ)

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