TY - JOUR
T1 - InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.
AU - Berg, Martin
AU - Persson, Karl-Magnus
AU - Wu, Jun
AU - Lind, Erik
AU - Sjöland, Henrik
AU - Wernersson, Lars-Erik
PY - 2014
Y1 - 2014
N2 - Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a [Formula: see text] cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.
AB - Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a [Formula: see text] cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.
U2 - 10.1088/0957-4484/25/48/485203
DO - 10.1088/0957-4484/25/48/485203
M3 - Article
C2 - 25382271
SN - 0957-4484
VL - 25
JO - Nanotechnology
JF - Nanotechnology
IS - 48
M1 - 485203
ER -