Integrated Test Scheduling, Test Parallelization and TAM Design

Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages397-404
ISBN (Print)0-7695-1825-7
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventIEEE Asian Test Symposium ATS02 - Guam, United States
Duration: 2002 Nov 182002 Nov 20

Publication series

Name
ISSN (Print)1081-7735

Conference

ConferenceIEEE Asian Test Symposium ATS02
Country/TerritoryUnited States
CityGuam
Period2002/11/182002/11/20

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • test access mechanism
  • TAM
  • TAM routing
  • test scheduling
  • scan chain partitioning
  • test conflicts
  • power constraints

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