TY - JOUR
T1 - Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
AU - Persson, Anton E. O.
AU - Zhu, Zhongyunshen
AU - Athle, Robin
AU - Wernersson, Lars-Erik
PY - 2022/6
Y1 - 2022/6
N2 - We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.
AB - We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.
U2 - 10.1109/LED.2022.3171597
DO - 10.1109/LED.2022.3171597
M3 - Article
SN - 0741-3106
VL - 43
SP - 854
EP - 857
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 6
ER -