Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

Anton E. O. Persson; Zhongyunshen Zhu; Robin Athle; Lars-Erik Wernersson

doi:10.1109/LED.2022.3171597

Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

Anton E. O. Persson, Zhongyunshen Zhu, Robin Athle, Lars-Erik Wernersson

NanoLund: Centre for Nanoscience

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Abstract

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.

Original language	English
Pages (from-to)	854 - 857
Journal	IEEE Electron Device Letters
Volume	43
Issue number	6
DOIs	https://doi.org/10.1109/LED.2022.3171597
Publication status	Published - 2022 Jun

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

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10.1109/LED.2022.3171597

Peer-reviewed accepted manuscriptAccepted author manuscript, 4.14 MB

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@article{816728fc017944b8a55fd961eae1417b,

title = "Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon",

abstract = "We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.",

author = "Persson, \{Anton E. O.\} and Zhongyunshen Zhu and Robin Athle and Lars-Erik Wernersson",

year = "2022",

month = jun,

doi = "10.1109/LED.2022.3171597",

language = "English",

volume = "43",

pages = "854 -- 857",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

AU - Persson, Anton E. O.

AU - Zhu, Zhongyunshen

AU - Athle, Robin

AU - Wernersson, Lars-Erik

PY - 2022/6

Y1 - 2022/6

N2 - We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.

AB - We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.

UR - https://www.scopus.com/pages/publications/85129367060

U2 - 10.1109/LED.2022.3171597

DO - 10.1109/LED.2022.3171597

M3 - Article

SN - 0741-3106

VL - 43

SP - 854

EP - 857

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 6

ER -

Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

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Ferroelectric Memristors - Materials, Interfaces and Applications

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