Low Power Optimization of Bit-Serial Digital Filters

Pontus Åström, Peter Nilsson, Mats Torkelson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

1 Citation (SciVal)

Abstract

A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption
Original languageEnglish
Title of host publicationTenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages229-232
ISBN (Print)0-7803-4283-6
DOIs
Publication statusPublished - 1997
EventTenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97) - Portland, Oregon, United States
Duration: 1997 Sep 71997 Sep 10

Conference

ConferenceTenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)
Country/TerritoryUnited States
CityPortland, Oregon
Period1997/09/071997/09/10

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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