Low Power Optimization of Bit-Serial Digital Filters

Pontus Åström; Peter Nilsson; Mats Torkelson

doi:10.1109/ASIC.1997.617011

Low Power Optimization of Bit-Serial Digital Filters

Pontus Åström, Peter Nilsson, Mats Torkelson

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

1 Citation (SciVal)

Abstract

A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption

Original language	English
Title of host publication	Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	229-232
ISBN (Print)	0-7803-4283-6
DOIs	https://doi.org/10.1109/ASIC.1997.617011
Publication status	Published - 1997
Event	Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97) - Portland, Oregon, United States Duration: 1997 Sep 7 → 1997 Sep 10

Conference

Conference	Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)
Country/Territory	United States
City	Portland, Oregon
Period	1997/09/07 → 1997/09/10

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/ASIC.1997.617011

Cite this

@inproceedings{6cc403b4ae86485fbe4cd5c05666294c,

title = "Low Power Optimization of Bit-Serial Digital Filters",

abstract = "A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption",

author = "Pontus {\AA}str{\"o}m and Peter Nilsson and Mats Torkelson",

year = "1997",

doi = "10.1109/ASIC.1997.617011",

language = "English",

isbn = "0-7803-4283-6",

pages = "229--232",

booktitle = "Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC{\textquoteright}97) ; Conference date: 07-09-1997 Through 10-09-1997",

}

Åström, P, Nilsson, P & Torkelson, M 1997, Low Power Optimization of Bit-Serial Digital Filters. in Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 229-232, Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97), Portland, Oregon, United States, 1997/09/07. https://doi.org/10.1109/ASIC.1997.617011

Low Power Optimization of Bit-Serial Digital Filters. / Åström, Pontus; Nilsson, Peter; Torkelson, Mats.

Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.. IEEE - Institute of Electrical and Electronics Engineers Inc., 1997. p. 229-232.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Low Power Optimization of Bit-Serial Digital Filters

AU - Åström, Pontus

AU - Nilsson, Peter

AU - Torkelson, Mats

PY - 1997

Y1 - 1997

N2 - A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption

AB - A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption

U2 - 10.1109/ASIC.1997.617011

DO - 10.1109/ASIC.1997.617011

M3 - Paper in conference proceeding

SN - 0-7803-4283-6

SP - 229

EP - 232

BT - Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)

Y2 - 7 September 1997 through 10 September 1997

ER -

Low Power Optimization of Bit-Serial Digital Filters

Abstract

Conference

Subject classification (UKÄ)

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Cite this