Abstract
A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption
Original language | English |
---|---|
Title of host publication | Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings. |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Pages | 229-232 |
ISBN (Print) | 0-7803-4283-6 |
DOIs | |
Publication status | Published - 1997 |
Event | Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97) - Portland, Oregon, United States Duration: 1997 Sept 7 → 1997 Sept 10 |
Conference
Conference | Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97) |
---|---|
Country/Territory | United States |
City | Portland, Oregon |
Period | 1997/09/07 → 1997/09/10 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering