Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon

Research output: Contribution to journalArticlepeer-review

11 Citations (SciVal)
134 Downloads (Pure)


III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore’s law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to 0.01 μm2 enabling realization of dense memory (1T1R) cross-point arrays on silicon.
Original languageEnglish
Article number9154433
Pages (from-to)1432-1435
JournalIEEE Electron Device Letters
Issue number9
Publication statusPublished - 2020 Aug 3

Subject classification (UKÄ)

  • Nano Technology


  • Resistive random access memory (RRAM)
  • 1T1R
  • Vertical nanowire
  • Gate-All-Around MOSFET
  • ITO


Dive into the research topics of 'Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon'. Together they form a unique fingerprint.

Cite this