Memory architecture evaluation for video encoding on enhanced embedded processors

Ali Iranpour; Krzysztof Kuchcinski

doi:10.1007/11796435_32

Memory architecture evaluation for video encoding on enhanced embedded processors

Ali Iranpour, Krzysztof Kuchcinski

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

Original language	English
Title of host publication	Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science)
Publisher	Springer
Pages	309-320
Volume	4017
ISBN (Print)	978-3-540-36410-8
DOIs	https://doi.org/10.1007/11796435_32
Publication status	Published - 2006
Event	Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop - Samos, Greece Duration: 2006 Jul 17 → 2006 Jul 20

Publication series

Name
Volume	4017
ISSN (Print)	1611-3349
ISSN (Electronic)	0302-9743

Conference

Conference	Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop
Country/Territory	Greece
City	Samos
Period	2006/07/17 → 2006/07/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Subject classification (UKÄ)

Computer Sciences

Access to Document

10.1007/11796435_32

Cite this

@inproceedings{b1ef462975f242fe98a2a2059e126b75,

title = "Memory architecture evaluation for video encoding on enhanced embedded processors",

abstract = "In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.",

author = "Ali Iranpour and Krzysztof Kuchcinski",

year = "2006",

doi = "10.1007/11796435\_32",

language = "English",

isbn = "978-3-540-36410-8",

volume = "4017",

publisher = "Springer",

pages = "309--320",

booktitle = "Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science)",

address = "Germany",

note = "Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop ; Conference date: 17-07-2006 Through 20-07-2006",

}

Iranpour, A & Kuchcinski, K 2006, Memory architecture evaluation for video encoding on enhanced embedded processors. in Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science). vol. 4017, Springer, pp. 309-320, Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop, Samos, Greece, 2006/07/17. https://doi.org/10.1007/11796435_32

Memory architecture evaluation for video encoding on enhanced embedded processors. / Iranpour, Ali; Kuchcinski, Krzysztof.
Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science). Vol. 4017 Springer, 2006. p. 309-320.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Memory architecture evaluation for video encoding on enhanced embedded processors

AU - Iranpour, Ali

AU - Kuchcinski, Krzysztof

PY - 2006

Y1 - 2006

N2 - In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

AB - In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

UR - https://www.scopus.com/pages/publications/33746668079

U2 - 10.1007/11796435_32

DO - 10.1007/11796435_32

M3 - Paper in conference proceeding

SN - 978-3-540-36410-8

VL - 4017

SP - 309

EP - 320

BT - Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science)

PB - Springer

T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop

Y2 - 17 July 2006 through 20 July 2006

ER -

Memory architecture evaluation for video encoding on enhanced embedded processors

Abstract

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