Modification of SOVA-based Algorithms for Efficient Hardware Implementation

Lay-Hong Ang; Wee-Guan Lim; Matthias Kamuf

doi:10.1109/VETECS.2010.5493927

Modification of SOVA-based Algorithms for Efficient Hardware Implementation

Lay-Hong Ang, Wee-Guan Lim, Matthias Kamuf

Departments at LTH

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficient hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offspring, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule ( BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.

Original language	English
Title of host publication	IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	1-5
DOIs	https://doi.org/10.1109/VETECS.2010.5493927
Publication status	Published - 2010
Event	IEEE Vehicular Technology Conference (VTC Spring), 2010 - Taipei, Taiwan Duration: 2010 May 16 → 2010 May 19 Conference number: 71

Publication series

Name
ISSN (Print)	1550-2252

Conference

Conference	IEEE Vehicular Technology Conference (VTC Spring), 2010
Country/Territory	Taiwan
City	Taipei
Period	2010/05/16 → 2010/05/19

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/VETECS.2010.5493927

Cite this

@inproceedings{6edb900fa52340f0b3bee05543c4c44d,

title = "Modification of SOVA-based Algorithms for Efficient Hardware Implementation",

abstract = "In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficient hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offspring, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule ( BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.",

author = "Lay-Hong Ang and Wee-Guan Lim and Matthias Kamuf",

year = "2010",

doi = "10.1109/VETECS.2010.5493927",

language = "English",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "1--5",

booktitle = "IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010",

address = "United States",

note = "IEEE Vehicular Technology Conference (VTC Spring), 2010 ; Conference date: 16-05-2010 Through 19-05-2010",

}

Ang, L-H, Lim, W-G & Kamuf, M 2010, Modification of SOVA-based Algorithms for Efficient Hardware Implementation. in IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 1-5, IEEE Vehicular Technology Conference (VTC Spring), 2010, Taipei, Taiwan, 2010/05/16. https://doi.org/10.1109/VETECS.2010.5493927

Modification of SOVA-based Algorithms for Efficient Hardware Implementation. / Ang, Lay-Hong; Lim, Wee-Guan; Kamuf, Matthias.
IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010. IEEE - Institute of Electrical and Electronics Engineers Inc., 2010. p. 1-5.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Modification of SOVA-based Algorithms for Efficient Hardware Implementation

AU - Ang, Lay-Hong

AU - Lim, Wee-Guan

AU - Kamuf, Matthias

N1 - Conference code: 71

PY - 2010

Y1 - 2010

N2 - In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficient hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offspring, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule ( BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.

AB - In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficient hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offspring, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule ( BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.

U2 - 10.1109/VETECS.2010.5493927

DO - 10.1109/VETECS.2010.5493927

M3 - Paper in conference proceeding

SP - 1

EP - 5

BT - IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Vehicular Technology Conference (VTC Spring), 2010

Y2 - 16 May 2010 through 19 May 2010

ER -

Modification of SOVA-based Algorithms for Efficient Hardware Implementation

Abstract

Publication series

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